As circuit designs continue to increase in performance and complexity, the design of such circuits becomes increasingly difficult and time consuming. A conventional electrical circuit may include hundreds or even thousand of discrete components, often in the form of interconnected integrated circuits. Each of these components may include a significant number of pins, allowing the components to be electrically coupled by a mesh of wires, traces, or other electrically conductive paths.
The task of designing an individual integrated circuit may be even more complex, as an integrated circuit often contains hundreds of thousands or even millions of individual transistors that form functional blocks. Electrical paths within the integrated circuit are coupled to “ports” associated with the functional blocks.
A designer often employs computer-aided techniques to aid the design, simulation, and verification of an electrical circuit. For example, the designer may utilize one or more software programs, also referred to as circuit design “tools” or “utilities,” to define the electrical circuit at an abstract or functional level. These tools typically provide extensive software libraries of electrical components, and present an interface with which the designer is able to graphically develop the circuit. In particular, the designer interacts with the interface to graphically form of one or more schematic diagrams having interconnected components or functional blocks.
Alternatively, the designer may utilize an editor or other software application to describe the circuit in accordance with a hardware description language (HDL). Examples of widely-used HDLs include the Very high-speed integrated circuits Hardware Description Language (VHDL) and Verilog™, which is described in the IEEE Verilog 1364-2000 standard. These languages support syntaxes that appear similar to software programming languages, such as C++ and Java, and allow the designer to define and simulate the circuit by using high-level code to describe the structure and behavior of the circuit.
In order to further aid the validation and debugging of the circuits being designed, these computer aided techniques typically include functionality to produce a “netlist” that describes the defined signals that interconnect the circuit components. A typical netlist report generated by a conventional circuit design tool displays the signals defined for the circuit in alphabetical order. The following table illustrates a portion of an example netlist:
TABLE 1Signal NameInstance NamePhysical Pin NamePart NameA20GATER621RES_SMA20GATEU1Y22COMP_CONN_MCLK1R301RES_SM.1CLK1U2P17CONN_COMP_L1CLK1P29PA838383
Using netlist reports for validation of the interconnectivity of the circuit can be cumbersome. In particular, the designer may spend a significant amount of time crosschecking the signals listed alphabetically by the netlist report with the interconnected components defined by the schematic diagrams or the hardware description language. This process is even more difficult for complex circuits having hundreds or thousands of signals.